C2D + Prime95 crashar oavsett vad jag gör.. :(

så ni säger att det här problemet beror på felaktigheter i de tidigaste revisionerna av processorn?

exempelvis i extreme techs forum så uppkommer juh andra frågår till detta... går det då att fixa med en bios uppdatering eller är det processorn i sig som måste uppdateras....

en intressant notering från intels document.....

AI20. FP Inexact-Result Exception Flag May Not Be Set

Problem:
When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs. However, other actions taken by the processor (invoking the software exception handler if the exception is unmasked) are not affected. This erratum can only occur if one of the following FST instructions is one or two instructions after the floatingpoint operation which causes the precision exception:

* FST m32real
* FST m64real
* FSTP m32real
* FSTP m64real
* FSTP m80real
* FIST m16int
* FIST m32int
* FISTP m16int
* FISTP m32int
* FISTP m64int
* FISTTP m16int
* FISTTP m32int
* FISTTP m64int

Note that even if this combination of instructions is encountered, there is also a dependency on the internal pipelining and execution state of both instructions in the processor.

Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it happens frequently, and produces a rounded result acceptable to most applications. The PE bit of the FPU status word may not always be set upon receiving an inexact-result exception. Thus, if these exceptions are unmasked, a floating-point error exception handler may not recognize that a precision exception occurred. Note that this is a "sticky" bit, i.e., once set by an inexact-result condition, it remains set until cleared by software.

Workaround: This condition can be avoided by inserting three non-floating-point instructions between the two floating-point instructions.

Status:
For the steppings affected, see the Summary Tables of Changes.

The Specification Changes listed in this section apply to the following documents:

* Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence
* IA-32 Intel® Architecture Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B

All Specification Changes will be incorporated into a future version of the appropriate Intel® Core™2 Extreme and Intel® Core™2 Duo Desktop Processor documentation.

det hela blir juh en mer intressant.. då fler en jag borde råkat ut för detta...